From Photons to Pixels to Bits (Many Bits): End-to-End HDR on FPGA

Real scenes do not respect a sensor’s dynamic range. A loading dock at noon, oncoming headlights at night, a weld arc next to dark metal – the information that matters often sits at both ends of the histogram at once. Capturing it is one problem. Moving and processing the data it produces, in real time, is another – because every added bit of dynamic range has to be carried through the entire chain.

At ImagingNext 2026, Alex Lopich, Director of Engineering at Altera, presents “From Photons to Pixels to Bits (Many Bits): End-to-End HDR on FPGA” – a session that follows a high-dynamic-range imaging pipeline end to end, implemented on FPGA.

About Alex Lopich

Alex Lopich has over 20 years of experience in vision, video, and sensor design. He gained his PhD in Electrical and Electronic Engineering from the University of Manchester and has held engineering, research, and leadership roles developing smart sensors, imaging systems, AI acceleration IPs, and solutions for computer and machine vision. He holds multiple patents and peer-reviewed publications, and currently leads the engineering team at Altera developing solutions for video and vision applications.

Why this matters now

HDR is a system problem, not a sensor feature. Extended dynamic range increases bit depths and data rates, and the processing that turns raw capture into usable output has to keep up at line rate, within tight latency budgets. That is what makes the choice of processing platform an architectural decision: it determines where in the pipeline dynamic range is preserved, where it is compressed, and how deterministic the timing of the whole chain is. For vision systems feeding real-time decisions, those tradeoffs shape the design as much as the sensor choice does.

Lopich has spent over 20 years in vision, video, and sensor design. He holds a PhD in Electrical and Electronic Engineering from the University of Manchester, along with multiple patents and peer-reviewed publications on smart sensor design and novel image processing architectures. He has developed smart sensors, imaging systems, and AI acceleration IPs, and today leads the engineering team at Altera building solutions for video and vision applications.

What you’ll take away

• A view of an HDR pipeline end to end – from photon capture through processing to the bits that leave the device.
• Where dynamic range is won and lost along the chain, and what that means for bandwidth and bit-depth budgets.
• What FPGAs bring to real-time HDR processing, and how the tradeoffs compare against other processing platforms.