SLVS-EC v2.0 RX IP Core for Xilinx

Description

The SLVS-EC RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly-efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC Standard v1.2 and v2.0 with 1, 2, 4, 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.

Supported Standard and Features:

The IP Core is available for the following devices:
• Xilinx Artix-7™
• Xilinx Kintex-7™
• Xilinx Zynq-7000™ SoC
• Xilinx Kintex UltraScale™
• Xilinx Kintex UltraScale+™
• Xilinx Zynq UltraScale+™ MPSoC
• Kria™ Robotics Starter Kit

An appropriate Evaluation Kit is available separately. Compatibility to further devices on request.