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SLVS-EC RX IP Core Source Edition

Customize your FPGA image pipeline with the SLVS-EC RX IP Core Source Edition, supporting high-speed Sony sensor integration and editable source code.

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Product Number: 28827
Category: SLVS-EC FPGA IP

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SLVS-EC RX IP Core Source Edition

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Product Summary

Source-editable IP Core for SLVS-EC sensor integration and advanced FPGA imaging workflows.

SLVS-EC RX IP Core Source Edition Highlights

  • Modifiable source version
  • Supports SLVS-EC v1.2 to v3.0
  • Dynamic pixel format conversion
  • FPGA-ready for AMD Xilinx platforms

Targeted Applications

  • Custom camera designs
  • FPGA-based image pipelines
  • SLVS-EC sensor evaluation
  • Advanced embedded vision

Product Specifications

ManufacturerManufacturer

FRAMOS

Product TypeProduct Type

IP Core, Source Code (VHDL, Verilog)

SpecificationSpecification

Supports Sony SLVS-EC up to v3.0 standard, Receiver FPGA module performing byte-to-pixel conversion from incoming SLVS-EC data stream

Target Device TypeTarget Device Type

FPGA, SoC, Supported AMD Architectures: 7-Series FPGA and SoC family, Ultrascale™ FPGA family, Ultrascale+™ FPGA and SoC family, Kria™ K26 SOM, Versal™ family

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Description

The SLVS-EC RX IP Core Source Edition by FRAMOS enables developers to integrate SLVS-EC-compatible Sony image sensors with their FPGA-based designs while retaining access to modifiable source code for customization. Supporting up to 8 configurable data lanes and multiple pixel depths from 8 to 16 bits, this IP Core allows dynamic mode switching and high-speed image data handling with minimal latency. The source edition adheres to SLVS-EC v1.2, v2.0, and v3.0 standards and includes full support for embedded metadata, CRC/ECC verification, and ROI overlapping. Compatible with AMD Xilinx platforms including Artix-7, Kintex-7, Zynq-7000, UltraScale, and Kria K26, it ensures flexible deployment across a wide range of FPGA environments. Developers benefit from full visibility and customization potential, making this version ideal for unique imaging workflows or proprietary data handling methods. With its source-level accessibility and broad compatibility, this IP Core accelerates innovation and supports highly specialized machine vision system designs.

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