FRAMOS SLVS-EC RX IP CORE

Shorten the time-to-market and improve performance for vision development on AMD-Xilinx FPGAs and AMD-Xilinx SoCs with integrated FPGA.
FRAMOS SLVS-EC RX IP CORE

What is the SLVS-EC RX IP Core?

The FRAMOS SLVS-EC RX IP Core is a receiver FPGA module that handles the byte-to-pixel conversion of the incoming image data stream. The IP Core outputs pixel data via Parallel Pixel Interface (PPI) that can be simply connected to customer’s FPGA logic. Expect versatile support for all SONY sensors that support SLVS-EC version 1.2, 2.0, and 3.0 at the maximum bit rate, regardless of the required number of lanes or bit depth.

Why use the SLVS-EC RX IP Core?

The FRAMOS SLVS-EC RX IP Core enables embedded vision system architects and engineers to realize the full potential of high-resolution image sensors. The IP Core unlocks the maximum speed of Sony’s high-bandwidth image sensor interface SLVS-EC up to version 3.0 for crystal-sharp, high-resolution imaging applications.

What does SLVS-EC stand for and what is it good for?

Sony’s Scalable Low Voltage Signaling with Embedded Clock (SLVS-EC) interface standard has emerged as the preferred interface for high-resolution and high-speed image sensors from Sony, enabling higher throughput, greater signal integrity, and simpler designs. Engineers developing solutions using AMD-Xilinx FPGAs and SoCs benefit vastly by using FRAMOS’ SLVS-EC RX IP Core, Evaluation Kit, and tested example designs. Device builders and camera vendors can de-risk the design while reaping the benefits of Sony’s latest high-speed interface, thus speeding up the vision-system building process.

7 Key Benefits of our IP Core

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Byte-to-pixel conversion for SLVS-EC v1.2/v2.0 /v3.0

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De-risk integration, reduce time to market

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Reference implementation for evaluation and guidance

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Flexible Lane Support in one IP Core

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Support for all common RAW bit-depths

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Error correction and ROI overlap support

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AXI4-Lite communication and control

While benefitting from the outstanding sensor performance, SLVS-EC’s technological advantages allow significantly simplified designs while extending cable lengths and maintaining signal integrity at high data rates. The SLVS-EC RX IP Core for AMD-Xilinx FPGAs and SoCs provides a trusted, known-good implementation of Sony’s preferred interface to advanced image sensors. FRAMOS offers help with the SLVS-EC to keep internal development teams focused on their core competencies. 

SLVS-EC RX IP Core for AMD FPGAs

The FRAMOS SLVS-EC RX IP Core handles the byte-to-pixel conversion of the incoming image data stream. The IP Core expects data from the AMDXilinx transceivers on the input, and provides the customer’s FPGA code with a parallel Pixel Interface (PPI). Expect versatile support for all SONY sensors that support SLVS-EC version 1.2, 2.0 and 3.0, at the maximum bit rate, regardless of the number of lanes or bit depth that are required.

IP Core
  • Encrypted RTL
  • Source Code Options Available
  • Simulation Environment (ModelSim)
Documentation
  • User Manual
  • Reference Design Application Note
Supported AMD Architectures
  • UltraScale™ FPGA family
  • 7-Series FPGA and SoC family
  • Ultrascale+™ FPGA and SoC family
  • Kria™ K26 SOM
  • Versal™ family
Supported devices are available on request.
PARAMETER
VALUE
Product Name
SLVS-EC RX IP Core for AMD FPGAs
Standard Version
SLVS-EC v1.2, v2.0, v3.0
Type
Receiver (RX)
Control Interface
AXI4-Lite
Input Interface
SLVS-EC v1.2, v2.0, v3.0
Lanes Supported
1, 2, 4, 8 (configurable by user and depending on the support of the hardware)
Baud Grade(s)
[1]: 1.2 Gbps, [2]: 2.5 Gbps, [3]: 5 Gbps, [4]: 10 Gbps
Pixel Format(s)
8,10,12,14,16 bits per pixel (RAW) (Dynamic Mode Change)
Dynamic Mode Change
Yes (Pixel Format)
CRC / ECC
Supported (Configurable)
Embedded Data
Supported
ROI Overlapping
Supported

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